Ten years ago, IEEE ratified a new standard for Hardware Verification Language named SystemVerilog. Since then, SystemVerilog has come a long way. Millions of lines of code have been written in SystemVerilog to create testbenches for verification of thousands of designs. In early 2011, Accellera adopted Universion Verification Methodology (UVM), a library coded in SystemVerilog, aimed at enabling interoperability of the Verification IPs across SystemVerilog compilers and tools. Earlier this year (March 2015), Accellera donated UVM 1.2 standard to IEEE for adoption as a standard methodology for hardware verification. IEEE standardization of UVM is exected to boost its adoption across the industry.
At a time when the electronic industry is investing heavily in SystemVerilog, any idea of creating a new verification language might seem outrightly foolish. Yet we see attempts year after year to create alternate solutions for verification. The past few years have seen emergence of SCV, trusster, pyHVL, cocotb and SystemC-UVM to name a few. It is pertinent to note that all of these are serious projects aimed at finding practical solutions to situations where SystemVerilog either fails completely is deemed to be too complex to deploy.
It is impossible to have a single HVL that can cover everything under the Sun. And importantly, with passage of time the verification domain has widened significantly. When the first SystemVerilog LRM was being drafted, industry was focussed on finding solutions for RTL verification. Lately, with the ever increasing Verification Gap, there is a growing clamor for verification at System Level. System level testbenches need to run much faster. Ability to coverify hardware and software is another system level desideratum.
Vlang aims to address the challenges posed by System Level verification while keeping interoperability with RTL simulations. Vlang takes a multi-pronged approach to faster stimulus generation. First of all, Vlang compiles to native machine code. Well, there are SystemVerilog compilers that too compile to native machine code, but Vlang creates optimized code that would run an order of magnitude faster for most algorithms. This is so because SystemVerilog as a language has certain overheads (like some implicit events) to take care of. Vlang completely avoids such overheads and creates executables that can potentially match the speed of any algorithm coded in C or C++. Secondly, Vlang enables multi-core testbenches. In fact Vlang is the only Verification Language that provides for a multicore capable port of UVM.
One major issue with SystemVerilog is that the language does not come with a standard library.